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1 ? fn6521.1 isl84467 ultra low on-resistance, +1.65v to +4.5v, single supply, quad spdt (dual dpdt) analog switch the intersil isl84467 device is a low on-resistance, low voltage, bidirectional, quad spdt (dual dpdt) analog switch designed to operate from a single +1.65v to +4.5v supply. targeted applications include battery powered equipment that benefit from low r on (0.39 ) and fast switching speeds (t on = 33ns, t off = 16ns). the digital logic input is 1.8v logic-compatible when using a single +3v supply. with a supply voltage of 4.2v and logic high voltage of 2.85v at both logic inputs, the part draws only 12a max of icc current. cell phones, for example, often face asic functionality limitations. the number of analog input or gpio pins may be limited and digital geometries are not well suited to analog switch performance. this part may be used to ?mux-in? additional functionality while reducing asic design risk. the isl84467 is offered in small form factor package, alleviating board space limitations. the isl84467 consists of four sp dt switches. it is configured as a dual double-pole/double-throw (dpdt) device with two logic control inputs that control two spdt switches each. the configuration can be used as a dual differential 2-to-1 multiplexer/demultiplexer. features ? on-resistance (r on ) - v+ = +4.3v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.39 - v+ = +3.0v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.45 - v+ = +1.8v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.65 ?r on matching between channels . . . . . . . . . . . . . . . . . 0.05 ?r on flatness across signal range . . . . . . . . . . . . . . . 0.05 ? single supply operation . . . . . . . . . . . . . . . +1.65v to +4.5v ? low power consumption (pd) . . . . . . . . . . . . . . . . <0.68w ? fast switching action (v+ = +4.3v) -t on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33ns -t off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16ns ? break-before-make ? 1.8v logic compatible (+3v supply) ? low icc current when vinh is not at the v+ rail ? available in 16 ld 3x3 tqfn and 16 ld tssop packages ? esd hbm rating - com pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9kv - all othe r pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6kv ? pb-free (rohs compliant) applications ? battery-powered, handheld, and portable equipment - cellular/mobile phones - pagers - laptops, notebooks, palmtops ? portable test and measurement ? medical equipment ? audio and video switching related literature ? technical brief tb363 ?guidelines for handling and processing moisture sensitive surface mount devices (smds)? ? application note an557 ?recommended test procedures for analog switches? table 1. features at a glance isl84467 number of switches 4 sw quad spdt (dual dpdt) 4.3v r on 0.39w 4.3v t on /t off 33ns/16ns 3.0v r on 0.45w 3.0v t on /t off 34ns/18ns 1.8v r on 0.65w 1.8v t on /t off 50ns/25ns package 16 ld 3x3 tqfn, 16 ld tssop data sheet july 23, 2008 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2007, 2008. all rights reserved all other trademarks mentioned are the property of their respective owners..
2 fn6521.1 july 23, 2008 pinouts (note 1) isl84467 (16 ld tqfn) top view isl84467 (16 ld tssop) top view note: 1. switches shown for logic ?0? input. 1 3 4 15 nc1 in1-2 no2 com2 com1 no1 v+ nc4 16 14 13 2 12 10 9 11 6 578 com4 no4 in3-4 nc3 nc2 gnd no3 com3 14 15 16 9 13 12 11 10 1 2 3 4 5 7 6 8 no1 com1 nc1 in1-2 no2 com2 gnd nc2 v+ com4 no4 in3-4 nc3 com3 no3 nc4 truth table logic nc sw no sw 0onoff 1offon note: logic ?0? 0.5v. logic ?1? 1.4v with a 3v supply. pin descriptions pin function v+ system power supply input (+1.65v to +4.5v) gnd ground connection in digital control input com analog switch common pin no analog switch normally open pin nc analog switch normally closed pin ordering information part number (note) part marking temp. range (c) package (pb-free) pkg. dwg. # isl84467irtz 67tz -40 to +85 16 ld 3x3 tqfn l16.3x3a isl84467irtz-t* 67tz -40 to +85 16 ld 3x3 tqfn tape and reel l16.3x3a ISL84467IVZ 84467 ivz -40 to +85 16 ld tssop m16.173 ISL84467IVZ-t* 84467 ivz -40 to +85 16 ld tssop tape and reel m16.173 *please refer to tb347 for detai ls on reel specifications. note: these intersil pb-free plastic pack aged products employ special pb-free material sets, molding compounds/die attach materi als, and 100% matte tin plate plus anneal (e3 terminat ion finish, which is rohs compliant and compatible with both snpb and pb-free sold ering operations). intersil pb-free products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements o f ipc/jedec j std-020. isl84467
3 fn6521.1 july 23, 2008 absolute maximum rati ngs thermal information v+ to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 5.5v input voltages no, nc, in (note 2) . . . . . . . . . . . . . . . . . . . -0.5 to ((v+) + 0.5v) output voltages com (note 2) . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to ((v+) + 0.5v) continuous current no, nc, or com . . . . . . . . . . . . . . . . . 300ma peak current no, nc, or com (pulsed 1ms, 10% duty cycle, max) . . . . . . . . . . . . . . . . 500ma esd rating: human body model (com x ) . . . . . . . . . . . . . . . . . . . . . . . . .>9kv human body model (no x , nc x , in x , v+, gnd) . . . . . . . . . .>6kv machine model (com x ) . . . . . . . . . . . . . . . . . . . . . . . . . . . .>700v machine model (no x , nc x , in x , v+, gnd) . . . . . . . . . . . . .>300v charged device model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>1kv thermal resistance (typical) ja (c/w) tqfn package (note 3) . . . . . . . . . . . . . . . . . . . . . 70 tssop package (note 4) . . . . . . . . . . . . . . . . . . . . 115 maximum storage temperature range . . . . . . . . . . . -65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp operating conditions temperature range . . . . . . . . . . . . . . . . . . . . . . . . . -40c to +85c caution: do not operate at or near the maximum ratings listed fo r extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 2. signals on nc, no, in, or com exceeding v+ or gnd are clamped by internal diodes. limi t forward diode current to maximum curr ent ratings. 3. ja is measured in free air with the component mounted on a high ef fective thermal conductivity te st board with ?direct attach? fe atures. see tech brief tb379. 4. ja is measured with the component mounted on a low effective ther mal conductivity test board in free air. see tech brief tb379 fo r details. electrical specifications - 4.3v supply test conditions: v+ = +3.9v to +4.5v, gnd = 0v, v inh = 1.6v, v inl = 0.5v (note 5), unless otherwise specified. parameter test conditions temp (c) min (notes 6, 9) typ max (notes 6, 9) units analog switch characteristics analog signal range, v analog full 0 v+ v on-resistance, r on v+ = 3.9v, i com = 100ma, v no or v nc = 0v to v+ (see figure 5, note 10) 25 0.4 full 0.45 r on matching between channels, r on v+ = 3.9v, i com = 100ma, v no or v nc = voltage at max r on (notes 8, 10) 25 0.05 full 0.06 r on flatness, r flat(on) v+ = 3.9v, i com = 100ma, v no or v nc = 0v to v+ (notes 7, 10) 25 0.05 full 0.05 no or nc off leakage current, i no(off) or i nc(off) v+ = 4.5v, v com = 0.3v, 3v, v no or v nc = 3v, 0.3v 25 -70 70 na full -165 165 na com on leakage current, i com(on) v + = 4.5v, v com = 0.3v, 3v, or v no or v nc = 0.3v, 3v 25 -70 70 na full -165 165 na dynamic characteristics turn-on time, t on v+ = 3.9v, v no or v nc = 3.0v, r l =50 , c l = 35pf (see figure 1) 25 33 ns full 38 ns turn-off time, t off v+ = 3.9v, v no or v nc = 3.0v, r l =50 , c l = 35pf (see figure 1) 25 16 ns full 21 ns break-before-make time delay, t d v+ = 4.5v, v no or v nc = 3.0v, r l =50 , c l = 35pf (see figure 3) full 3 ns charge injection, q c l = 1.0nf, v g = 0v, r g = 0 ( see figure 2) 25 248 pc off isolation r l = 50 , c l = 5pf, f = 100khz, v com = 1v rms (see figure 4) 25 65 db isl84467
4 fn6521.1 july 23, 2008 crosstalk (channel-to-channel) r l = 50 , c l = 5pf, f = 100khz, v com = 1v rms (see figure 6) 25 -85 db total harmonic distortion f = 20hz to 20khz, v com = 2v p-p , r l = 600 25 0.008 % no or nc off capacitance, c off f = 1mhz, v no or v nc = v com = 0v (see figure 7) 25 38 pf com on capacitance, c com(on) f = 1mhz, v no or v nc = v com = 0v (see figure 7) 25 102 pf power supply characteristics power supply range full 1.65 4.5 v positive supply current, i+ v+ = +4.5v, v in = 0v or v+ 25 0.15 a full 1.4 a positive supply current, i+ v+ = +4.2v, v in = 2.85v 25 13 a digital input characteristics input voltage low, v inl full 0.5 v input voltage high, v inh full 1.6 v input current, i inh , i inl v+ = 4.5v, v in = 0v or v+ full -0.5 0.5 a electrical specifications - 3.0v supply test conditions: v+ = +2.7v to +3.3v, gnd = 0v, v inh = 1.4v, v inl = 0.5v (note 5), unless otherwise specified. parameter test conditions temp (c) min (notes 6, 9) typ max (notes 6, 9) units analog switch characteristics analog signal range, v analog full 0 v+ v on-resistance, r on v+ = 2.7v, i com = 100ma, v no or v nc = 0v to v+ (see figure 5, note 10) 25 0.55 0.75 full 0.85 r on matching between channels, r on v+ = 2.7v, i com = 100ma, v no or v nc = voltage at max r on (notes 8, 10) 25 0.08 0.19 full 0.22 r on flatness, r flat(on) v+ = 2.7v, i com = 100ma, v no or v nc = 0v to v+ (notes 7, 10) 25 0.07 0.15 full 0.15 no or nc off leakage current, i no(off) or i nc(off) v+ = 3.3v, v com = 0.3v, 3v, v no or v nc = 3v, 0.3v 25 1.1 na full 30 na com on leakage current, i com(on) v + = 3.3v, v com = 0.3v, 3v, or v no or v nc = 0.3v, 3v, or floating 25 1.5 na full 45 na dynamic characteristics turn-on time, t on v+ = 2.7v, v no or v nc = 1.5v, r l =50 , c l = 35pf (see figure 1) 25 34 ns full 39 ns turn-off time, t off v+ = 2.7v, v no or v nc = 1.5v, r l =50 , c l = 35pf (see figure 1) 25 18 ns full 23 ns break-before-make time delay, t d v+ = 3.3v, v no or v nc = 1.5v, r l =50 , c l = 35pf (see figure 3) full 3 ns charge injection, q c l = 1.0nf, v g = 0v, r g = 0 (see figure 2) 25 126 pc off isolation r l = 50 , c l = 5pf, f = 100khz, v com = 1v rms (see figure 4) 25 65 db electrical specifications - 4.3v supply test conditions: v+ = +3.9v to +4.5v, gnd = 0v, v inh = 1.6v, v inl = 0.5v (note 5), unless otherwise specified. (continued) parameter test conditions temp (c) min (notes 6, 9) typ max (notes 6, 9) units isl84467
5 fn6521.1 july 23, 2008 crosstalk (channel-to-channel) r l = 50 , c l = 5pf, f = 100khz, v com = 1v rms (see figure 6) 25 -85 db total harmonic distortion f = 20hz to 20khz, v com = 2v p-p , r l = 600 25 0.012 % no or nc off capacitance, c off f = 1mhz, v no or v nc = v com = 0v (see figure 7) 25 38 pf com on capacitance, c com(on) f = 1mhz, v no or v nc = v com = 0v (see figure 7) 25 102 pf power supply characteristics positive supply current, i+ v+ = 3.6v, v in = 0v or v+ 25 0.021 a full 0.72 a digital input characteristics input voltage low, v inl full 0.5 v input voltage high, v inh full 1.4 v input current, i inh , i inl v+ = 3.6v, v in = 0v or v+ full -0.5 0.5 a electrical specifications - 1.8v supply test conditions: v+ = +1.65v to +2v, gnd = 0v, v inh = 1.0v, v inl = 0.4v (note 5), unless otherwise specified. parameter test conditions temp (c) min (notes 6, 9) typ max (notes 6, 9) units analog switch characteristics analog signal range, v analog full 0 v+ v on-resistance, r on v+ = 1.8v, i com = 100ma, v no or v nc = 0v to v+ (see figure 5, note 10) 25 0.7 0.9 full 0.95 dynamic characteristics turn-on time, t on v+ = 1.65v, v no or v nc = 1.0v, r l =50 , c l = 35pf (see figure 1) 25 50 ns full 55 ns turn-off time, t off v+ = 1.65v, v no or v nc = 1.0v, r l =50 , c l = 35pf (see figure 1) 25 25 ns full 30 ns break-before-make time delay, t d v+ = 2.0v, v no or v nc = 1.0v, r l =50 , c l = 35pf (see figure 3) full 8 ns charge injection, q c l = 1.0nf, v g = 0v, r g = 0 ( see figure 2) 25 48 pc digital input characteristics input voltage low, v inl full 0.4 v input voltage high, v inh full 1.0 v input current, i inh , i inl v+ = 2.0v, v in = 0v or v+ full -0.5 0.5 a notes: 5. v in = input voltage to perform proper function. 6. the algebraic convention, whereby the most negative value is a minimum and the most positive a ma ximum, is used in this data sheet. 7. flatness is defined as the diff erence between maximum and minimum value of on-r esistance over the specified analog signal ran ge. 8. r on matching between channels is calculated by s ubtracting the channel with the highest max r on value from the channel with lowest max r on value, between nc1 and nc2, nc3 and nc4 or between no1 and no2, no3 and no4. 9. parameters with min and/or max limits are 100% tested at +25 c, unless otherwise specified. temperature limits established by characterization and are not production tested. 10. limits established by characterization and are not production tested. electrical specifications - 3.0v supply test conditions: v+ = +2.7v to +3.3v, gnd = 0v, v inh = 1.4v, v inl = 0.5v (note 5), unless otherwise specified. (continued) parameter test conditions temp (c) min (notes 6, 9) typ max (notes 6, 9) units isl84467
6 fn6521.1 july 23, 2008 test circuits and waveforms logic input waveform is inverted for switches that have the opposite logic sense. figure 1a. measurement points repeat test for all switches. c l includes fixture and stray capacitance. figure 1b. test circuit figure 1. switching times figure 2a. measurement points figure 2b. test circuit figure 2. charge injection figure 3a. measurement points c l includes fixture and stray capacitance. figure 3b. test circuit figure 3. break-before-make time 50% t off 90% v+ 0v v no 0v t on logic input switch input switch output 90% v out v out v (no or nc) r l r l r on + ----------------------- - = switch input logic input v out r l c l com no or nc in 50 35pf gnd v+ c v out dv out on off on q = dv out x c l switch output logic input v+ 0v c l v out r g v g gnd com no or nc v+ c logic input in 90% v+ 0v t d logic input switch output 0v v out logic input com r l c l v out 35pf 50 v+ gnd v nx c no nc in isl84467
7 fn6521.1 july 23, 2008 detailed description the isl84467 is a bidirectional, quad single pole/double throw (spdt) analog switch t hat offers precise switching capability from a single 1.65v to 4.5v supply with low on-resistance (0.39 ) and high speed operation (t on = 33ns, t off = 16ns). the device is especially well suited for portable battery powered equipment due to its low operating supply voltage (1.65v), low power consumption (6.3w max), low leakage currents (165na max), and the tiny tqfn package. the ultra low on-resistance and r on flatness provide very low insertion loss and distortion to applications that require signal reproduction. external v+ series resistor for improved esd and latch-up immunity, intersil recommends adding a 100 resistor in series with the v+ power supply pin of the isl84467 ic (see figure 8). during an overvoltage transient event, such as occurs during system level iec 61000 esd testi ng, substrate currents can be generated in the ic that can tri gger parasitic scr structures to turn on, creating a low impedance path from the v+ power supply to ground. this will resu lt in a significant amount of current flow in the ic which c an potentially create a latch-up state or permanently damage the ic. the external v+ resistor limits the current duri ng this over-stress situation and has been found to prevent latch-up or destructive damage for many overvoltage transient events. under normal operation, the sub-microamp idd current of the ic produces an insignificant voltage drop across the 100 series resistor resulting in no impact to switch operation or performance. figure 4. off isolation test circuit figure 5. r on test circuit figure 6. crosstalk test circuit figure 7. capacitance test circuit test circuits and waveforms (continued) analyzer r l signal generator v+ c 0v or v+ no or nc com in gnd v+ c in gnd v nx v 1 r on = v 1 /100ma 100ma no or nc 0v or v+ com 0v or v+ analyzer v+ c no or nc signal generator r l gnd in 1 50 nc com com nc or no v+ c gnd no or nc com in impedance analyzer 0v or v+ isl84467
8 fn6521.1 july 23, 2008 . supply sequencing and overvoltage protection with any cmos device, proper power supply sequencing is required to protect the device from excessive input currents which might permanently damage the ic. all i/o pins contain esd protection diodes from the pin to v+ and to gnd (see figure 9). to prevent forward biasing these diodes, v+ must be applied before any input signals, and the input signal voltages must remain between v+ and gnd. if these conditions cannot be guaranteed, then precautions must be implemented to prohibit the current and voltage at the logic pin and signal pins from exceeding the maximum ratings of the switch. the following two methods can be used to provide additional protection to limit the current in the event that the voltage at a signal pin or logic pin goes below ground or above the v+ rail. logic inputs can be protected by adding a 1k resistor in series with the logic input (see figure 9). the resistor limits the input current below the threshold that produces permanent damage, and the sub-microamp input curr ent produces an insignificant voltage drop during normal operation. this method is not acceptable for the signal path inputs. adding a series resistor to the switch input defeats the purpose of using a low r on switch. connecting schottky diodes to the signal pins (as shown in figure 9) will shunt the fault current to the supply or to ground, thereby protecting the switch. these schottky diodes must be sized to handle the expected fault current. . power-supply considerations the isl84467 construction is typical of most single supply cmos analog switches, in that they have two supply pins: v+ and gnd. v+ and gnd drive the internal cmos switches and set their analog voltage limits. unlike switches with a 4.7v maximum supply voltage, the isl84467 5.5v maximum supply voltage provides plenty of room for the 10% tolerance of 4.3v supplies, as well as room for overshoot and noise spikes. the minimum recommended supply voltage is 1.65v. it is important to note that the input signal range, switching times, and on-resistance degrade at lower supply voltages. refer to the ?electrical specifications? tables starting on page 3 and the ?typical performance curves? starting on page 9 for details. v+ and gnd also power the internal logic and level shifters. the level shifters convert the in put logic levels to switched v+ and gnd signals to drive the analog switch gate terminals. this family of switches cannot be operated with bipolar supplies, because the input switching point becomes negative in this configuration. logic-level thresholds this switch family is 1.8v cmos compatible (0.5v and 1.4v) over a supply range of 3.0v to 4.5v (see figure 19). at 3.0v the v il level is about 0.53v. this is still above the 1.8v cmos guaranteed low output ma ximum level of 0.5v, but noise margin is reduced. the digital input stages draw supply current whenever the digital input voltage is not at one of the supply rails. driving the digital input signals from g nd to v+ with a fast transition time minimizes power dissipation. the isl84467 has been designed to minimize the supply current whenever the digital input voltage is not driven to the supply rails (0v to v+). for example, driving the device with 2.85v logic (0v to 2.85v) while operating with a 4.2v supply the device draws only 12a of current (see figure 17 for v in = 2.85v). figure 8. v+ series resistor for enhanced esd and latch-up immunity inx comx 100 no x nc x v+ gnd c optional protection resistor figure 9. overvoltage protection gnd v com v nx v+ in x optional protection resistor optional schottky diode optional schottky diode isl84467
9 fn6521.1 july 23, 2008 high-frequency performance in 50 systems, the isl84467 ha s a -3db bandwidth of 104mhz (see figure 22). the frequency response is very consistent over a wide v+ range, and for varying analog signal levels. an off switch acts like a capacitor and passes higher frequencies with less attenuation, resulting in signal feedthrough from a switch?s input to its output. off isolation is the resistance to this feedthrough, while crosstalk indicates the amount of feedthrough fr om one switch to another. figure 23 details the high off isolation and crosstalk rejection provided by this part. at 100khz, off isolation is about 65db in 50 systems, decreasing appro ximately 20db per decade as frequency increases. hi gher load impedances decrease off isolation and crosstalk rejection due to the voltage divider action of the switch off impedance and the load impedance. leakage considerations reverse esd protection diodes are internally connected between each analog-signal pin and both v+ and gnd. one of these diodes conducts if any analog signal exceeds v+ or gnd. virtually all the analog leakage current comes from the esd diodes to v+ or gnd. although the esd diodes on a given signal pin are identical and therefore fairly well balanced, they are reverse biased differently. each is biased by either v+ or gnd and the analog signal. this means their leakages will vary as the signal varies. the difference in the two diode leakages to the v+ and gnd pi ns constitutes the analog signal path leakage current. all analog leakage current flows between each pin and one of the supply terminals, not to the other switch terminal. this is why bot h sides of a given switch can show leakage currents of the same or opposite polarity. there is no connection between the analog signal paths and v+ or gnd. typical performance curves t a = +25c, unless otherwise specified. figure 10. on-resistance vs supply voltage vs switch voltage figure 11. on-resistance vs supply voltage vs switch voltage figure 12. on-resistance vs supply voltage vs switch voltage figure 13. on-resistance vs switch voltage 012345 r on ( ) v com (v) i com = 100ma 0.32 0.33 0.34 0.35 0.36 0.37 0.38 0.39 0.40 v+ = 4.5v v+ = 4.3v v+ = 3.9v r on ( ) v com (v) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 0.36 0.37 0.38 0.39 0.40 0.41 0.42 0.43 0.44 0.45 0.46 i com = 100ma v+ = 3.3v v+ = 3v v+ = 2.7v 00.51.01.52.0 0.4 0.5 0.6 0.7 0.8 r on ( ) v com (v) i com = 100ma v+ = 2v v+ = 1.8v v+ = 1.65v 012345 0.25 0.30 0.35 0.40 0.45 r on ( ) v com (v) v+ = 4.3v i com = 100ma +85c -40c +25c isl84467
10 fn6521.1 july 23, 2008 figure 14. on-resistance vs switch voltage figure 15. on-resistance vs switch voltage figure 16. on-resistance vs switch voltage figure 17. supply current vs vlogic voltage figure 18. charge injection vs swit ch voltage figure 19. digital sw itching point vs supply voltage typical performance curves t a = +25c, unless otherwise specified. (continued) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 0.30 0.35 0.40 0.45 0.50 r on ( ) v com (v) +85c -40c v+ = 3.3v i com = 100ma +25c 0 0.5 1.0 1.5 2.0 2.5 3.0 0.30 0.35 0.40 0.45 0.50 0.55 r on ( ) v com (v) +85c -40c v+ = 2.7v +25c i com = 100ma 0 0.5 1.0 1.5 2.o 0.35 0.40 0.45 0.50 0.55 0.60 0.65 0.70 r on ( ) v com (v) +85c -40c v+ = 1.8v i com = 100ma +25c i on (ma) v in1, v in 2 (v) v+ = 4.2v 12345 0 50 100 150 200 sweeping both logic inputs 0 q (pc) v com (v) -100 -50 0 50 100 150 200 250 012345 v+ = 1.8v v+ = 3v v+ = 4.3v v+ (v) v inh and v inl (v) 1.5 2.0 2.5 3.0 3.5 4.0 4.5 v inh v inl 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 isl84467
11 fn6521.1 july 23, 2008 figure 20. turn-on time vs supply voltage fi gure 21. turn-off time vs supply voltage figure 22. frequency response figure 23. crosstalk and off isolation die characteristics substrate potential (powered up): gnd (qfn paddle connection: to ground or float) transistor count: 228 process: si gate cmos typical performance curves t a = +25c, unless otherwise specified. (continued) t on (ns) v+ (v) 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 0 50 100 150 200 250 +85c -40c +25c t off (ns) v+ (v) 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 10 15 20 25 30 35 40 +85c -40c +25c frequency (hz) 0 -20 normalized gain (db) gain phase v+ = 3v 0 20 40 60 80 100 phase () 1m 10m 100m 600m v in = 0.2v p-p to 2v p-p r l = 50 frequency (hz) 1k 100k 1m 100m 500m 10k 10m -110 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 crosstalk (db) off isolation (db) 110 10 20 30 40 50 60 70 80 90 100 isolation crosstalk v+ = 4.3v isl84467
12 fn6521.1 july 23, 2008 thin shrink small outlin e plastic packages (tssop) notes: 1. these package dimensions are wi thin allowable dimensions of jedec mo-153-ab, issue e. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension ?d? does not include mold flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e1? does not includ e interlead flash or protrusions. interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. dimension ?b? does not include dambar protrusion. allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of ?b? dimension at maximum ma terial condition. minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. controlling dimension: millimeter. converted inch dimen- sions are not necessarily exact. (angles in degrees) index area e1 d n 123 -b- 0.10(0.004) c a m bs e -a- b m -c- a1 a seating plane 0.10(0.004) c e 0.25(0.010) b m m l 0.25 0.010 gauge plane a2 0.05(0.002) m16.173 16 lead thin shrink small outline plastic package symbol inches millimeters notes min max min max a - 0.043 - 1.10 - a1 0.002 0.006 0.05 0.15 - a2 0.033 0.037 0.85 0.95 - b 0.0075 0.012 0.19 0.30 9 c 0.0035 0.008 0.09 0.20 - d 0.193 0.201 4.90 5.10 3 e1 0.169 0.177 4.30 4.50 4 e 0.026 bsc 0.65 bsc - e 0.246 0.256 6.25 6.50 - l 0.020 0.028 0.50 0.70 6 n16 167 0 o 8 o 0 o 8 o - rev. 1 2/02 isl84467
13 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn6521.1 july 23, 2008 isl84467 thin quad flat no-lead plastic package (tqfn) thin micro lead frame pl astic package (tmlfp) index d1/2 d1 d/2 d e1/2 e/2 e a 2x 0.15 b c 0.10 b a mc a n seating plane n 6 3 2 2 3 e 1 1 0.08 for odd terminal/side for even terminal/side c c section "c-c" nx b a1 c 2x c 0.15 0.15 2x b 0 ref. (nd-1)xe (ne-1)xe ref. 5 a1 4x p a c c 4x p b 2x a c 0.15 a2 a3 d2 d2 e2 e2/2 terminal tip side view top view 7 bottom view 7 5 c l c l e e e1 2 nx k nx b 8 nx l 8 8 9 area 9 4x 0.10 c / / 9 (datum b) (datum a) area index 6 area n 9 corner option 4x l1 l 10 l1 l 10 l16.3x3a 16 lead thin quad flat no-lead plastic package symbol millimeters notes min nominal max a 0.70 0.75 0.80 - a1 - - 0.05 - a2 - - 0.80 9 a3 0.20 ref 9 b 0.18 0.23 0.30 5, 8 d 3.00 bsc - d1 2.75 bsc 9 d2 1.35 1.50 1.65 7, 8, 10 e 3.00 bsc - e1 2.75 bsc 9 e2 1.35 1.50 1.65 7, 8, 10 e 0.50 bsc - k0.20 - - - l 0.30 0.40 0.50 8 n162 nd 4 3 ne 4 3 p- -0.609 --129 rev. 0 6/04 notes: 1. dimensioning and tolerancing conform to asme y14.5-1994. 2. n is the number of terminals. 3. nd and ne refer to the number of terminals on each d and e. 4. all dimensions are in millimeters. angles are in degrees. 5. dimension b applies to the meta llized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. the pin #1 identifier may be either a mold or mark feature. 7. dimensions d2 and e2 are fo r the exposed pads which provide improved electrical and thermal performance. 8. nominal dimensions are prov ided to assist with pcb land pattern design efforts, see intersil technical brief tb389. 9. features and dimensions a2, a3, d1, e1, p & are present when anvil singulation method is used and not present for saw singulation. 10. compliant to jedec mo-220weed-2 issue c, except for the e2 and d2 max dimension.

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